This invention relates to a high speed logic driver circuit, and more particularly to an active collector circuit which is capable of output dotting.
With advances in modern technology, increasing emphasis is being placed on system operating speed. One area in which operating speeds have become of paramount importance is in digital circuitry. In complex digital systems, it is often necessary that a plurality of stations be able to share a single communications buss, or common buss. In designing a common buss system, it has heretofore been necessary to reach a compromise between operating speed and system flexibility. This can be more clearly understood by referring to FIGS. 1 and 2.
In FIG. 1 an open collector-type driver circuit is illustrated. The load on the driver is represented by capacitor C. In response to a high level input at terminal A, transistors 10 and 20 will be turned on and V.sub.out will be at a low level. In response to a low level input at terminal A, transistors 10 and 20 will turn off and V.sub.out may assume a high level. This circuit is advantageous in that its output may be dotted with other circuits of this type. In other words, a plurality of driver circuits of the type shown in FIG. 1 may have their V.sub.out connected together so that the load may be driven to a low level if anyone of the plurality of commonly connected driver circuits has a low output voltage. The current drawn from any of the other driver circuits which may be in a high state can be kept to a minimum by providing a large resistance R. Even though the open collector circuit of FIG. 1 is advantageous in that it provides a dotting capability, it is unsatisfactory since the transition from low to high level output signals is very slow, being determined by the time constant RC. In high speed communications systems, this slow transition time is unacceptable.
An alternative to the slow-speed circuit of FIG. 1 is shown in FIG. 2. This circuit is known as a "THREE-STATE PUSH-PULL DRIVER" described in IBM Technical Disclosure Bulletin, Vol. 21, No. 1, June 1978, p. 172. The disadvantages of slow up-transition times have been eliminated by providing pull-up transistor 16 so that both up and down transitions are accomplished very rapidly. Note that when the input signal at A is high, transistors 11 and 14 will be on, providing a low output state, while a low input will turn off transistors 11 and 14 and turn on transistor 16 to provide a high output. The disadvantage in such a circuit is that, when output dotting is attempted by connecting outputs in common, catastrophic currents may flow through the transistor 16 when the pull-down transistor from one of the other driver circuits is turned on. Thus, it is necessary to provide inhibit inputs so that transistor 16 may be turned off even in the presence of a low input signal at A. When the inhibit inputs are driven to a up level, transistors 12 and 18 will turn on and transistors 14 and 16 will be simultaneously off. The open circuit condition thus created at the output will permit one of the other driver circuits to take command of the common buss. The inhibit circuitry shown in FIG. 2 as well as the three-state control logic required to drive it adds to the complexity and cost of the circuit while decreasing its reliability.
A third alternative as shown in FIG. 3 and is known as a "DOTTABLE PUSH-PULL DRIVER" described in IBM Technical Disclosure Bulletin, Vol. 21, No. 1, June 1978, pp. 233 to 234. In this circuit, transistor 22 is a pull-up transistor and transistor 24 is a pull-down transistor for fast switching in either direction. Output dotting capability is provided by transistor 26. The operation of the circuit of FIG. 3 is as follows:
First, if the input signal at A is high, transistor 24 will be on and V will be lower than V.sub.ref. This will turn on transistor 26 which, in turn, will turn off transistor 22. The current draw in this state may be maintained at a low level by providing a very large resistance 28.
If the input signal at A switches down, transistor 24 will turn off and V.sub.out will begin rising at a rate determined by the RC time constant of resistor 28 and the capacitive load C. As soon as V.sub.out exceeds V.sub.ref, transistor 26 will turn off, transistor 18 will turn on and V.sub.out will rise rapidly until it reaches a value of V.sup.+ -V.sub.be where V.sub.be is the base-emitter voltage of transistor 22. At this point, transistor 22 will turn off and V.sub.out continues to increase to a value of V.sup.+ at a rate again determined by the RC time constant.
When another such driver is output dotted, the operation of the driver of FIG. 3 is substantially the same. That is, with V.sub.out at a high level, the pull down transistor 30 from a another driver may be switched on. This will discharge the capacitive load to turn on transistor 26 which, in turn, switches off transistor 22.
The circuit of FIG. 3 has been found useful in many applications, but is unacceptable in some instances because of the slow V.sub.out rise at the beginning and end of the up transition. More seriously, there is a substantial possibility that the circuit will fail to operate unless certain safeguards are taken, which safeguards will further hamper the circuit operation. For example, the operation of transistor 26 depends upon the potential V.sub.out decreasing below V.sub.ref. V.sub.ref is typically chosen to be approximately 1 volt while V.sup.+ may be approximately 3 volts. With V.sub.out in a high state, it is approximately equal to three volts. When one of the pull down transistors is turned on, V.sub.out will initially decrease and current will be supplied through transistor 22. The ability of the circuit of FIG. 3 to operate properly will depend upon the ability of the pull down transistor to draw off the current from the capacitive load at a rate faster than it will be supplied by transistor 22, as otherwise the potential will never decrease below V.sub.ref. The circuit may operate satisfactorily alone, but when one or two additional circuits are output dotted, there will be three transistors 22 all supplying current in parallel, and it is probable that this will be sufficient to prevent the voltage V.sub.out from ever dropping below V.sub.ref. Thus, if operable at all, the circuit of FIG. 3 is severely limited in its dotting capability.
As will be apparent from the above discussion of prior art driver circuits, there is a need for an active collector driver circuit which is capable of output dotting, is less complex and more reliable than previously used tri-state driver circuits and is also capable of high operating speeds.